In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The semiconductor wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
Reliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, the shrinking dimensions of interconnect in VLSI and ULSI technologies have placed additional demands on the processing capabilities. As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to sub-micron dimensions (e.g., less than 0.20 micrometers or less), whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increase. Many traditional deposition processes have difficulty achieving substantially void-free and seam-free filling of sub-micron structures where the aspect ratio exceeds 4:1.
Currently, copper and its alloys have become the metals of choice for sub-micron interconnect technology due to its lower resistivity. One problem with the use of copper is that copper diffuses into silicon, silicon dioxide, and other dielectric materials, which may compromise the integrity of devices. Therefore, conformal barrier layers become increasingly important to prevent copper diffusion. Copper might not adhere well to the barrier layer; therefore, a liner layer might need to be deposited between the barrier layer and copper. Conformal deposition of the liner layer is also important to provide good step coverage to assist copper adhesion and/or deposition.
Conformal deposition of the barrier layer on interconnect features by deposition methods, such as atomic layer deposition (ALD), needs to occur on clean surfaces to ensure good adhesion between the barrier layer and/or liner layer, and the material(s) the barrier layer deposited upon. Surface impurity can become a source of defects during the heating cycles of the substrate processing. Pre-treatment can be used to remove unwanted compounds from the substrate surface prior to barrier deposition. In addition, deposition by ALD might need surface pre-treatment to make the substrate surface easier to bond with the deposition precursor to improve the quality of barrier layer deposition.
Electro-migration (EM) is a well-known reliability problem for metal interconnects, caused by electrons pushing and moving metal atoms in the direction of current flow at a rate determined by the current density. EM in copper lines is a surface phenomenon. It can occur wherever the copper is free to move, typically at an interface where there is poor adhesion between the copper and another material, such as at the copper/barrier or copper/liner interface. The quality and conformality of the barrier layer and/or liner layer can certainly affect the EM performance of copper interconnect. It is desirable to perform the ALD barrier and liner layer deposition right after the surface pre-treatment, since the pre-treated surface might be altered if the surface is exposed to oxygen or other contaminants for a period of time.
A post-treatment after barrier and/or liner layer deposition prior to the deposition of copper can improve the adhesion between the barrier or liner layer with copper by removing impurities from the substrate surface. In addition, a post-treatment after barrier or liner layer deposition prior the deposition of a copper seed layer by electroless method can increase nucleation sites for copper seed layer deposition, which can improve the film quality of the copper seed layer.
In view of the foregoing, there is a need for integrated systems and methods that perform substrate surface treatment and film deposition for copper interconnect with improved metal migration performance and reduced void propagation.